Driver-decoder circuits are part of an integrated circuit that incorporates a memory. The memory typically includes an array of memory cells. A memory cell is activated by selecting its row line and raising the voltage of the row line while transferring data to or from its column line. A row address, typically binary, is presented to the memory circuit. During the precharge portion of a read or write cycle, the row driver-decoder circuit maintains all row lines at ground potential. The row driver-decoder circuit raises the voltage of an addressed row from ground potential to a non-ground potential, such as VDD, during the active portion of a read or write cycle. The row driver-decoder circuits maintain all non-addressed rows at ground potential during the active portion of the cycle. As memories increase in size, that is as memories incorporate more and more memory cells, address decoding and driver circuits become more complex, requiring more space and more time to decode an address. Speed improvements in the decoding circuits are desirable. As integrated circuits are manufactured using smaller and smaller line widths, the area available for row driver-decoder circuits is reduced. The row driver-decoder circuit is fabricated on the same pitch spacing as the row that is being decoded. In laying-out the row driver-decoder circuits on-pitch, the space constraints preclude some circuit designs.
In the prior art, a row decoder-driver circuit included a P-channel transistor that had its source connected to power supply VDD, and its gate grounded, thereby being maintained in an on state. In the on state and in the absence of any pulldown on the drain, the drain of the P-channel transistor was maintained in a logic high. When the appropriate address was received, the drain of the P-channel transistor was coupled to ground and pulled low at the rate which would discharge the capacitance associated with the node. However, node discharge was inhibited by the P-channel transistor continuing to be in the conductive state, thereby electrically coupling the node to VDD. The continuous P-channel transistor conduction resulted in relatively slow discharge of the capacitance associated with the node. In turn the rate of transition of a selected row line from ground potential to non-ground potential was relatively slow. In order to overcome the continuous P-channel transistor conduction, the gain of the transistor or transistors coupling the drain of the P-channel transistor to ground must be substantially greater than the gain of the P-channel transistor. This increases the nodal capacitance of the drain of the P-channel transistor and substantially increases the time necessary to precharge the node-to-VDD potential when any transistors coupling this node to ground are switched to the nonconductive state. As a result, the rate of transition of a selected row from VDD to ground was relatively slow. What is needed is a technique to rapidly charge and discharge the capacitance, and in turn rapidly transition the row line from ground potential to a non-ground potential or to rapidly transition from a non-ground potential to ground potential.